Non-volatile memory systems program data into memory cells and read the programmed data from the memory cells by biasing the memory cells with voltages at certain levels during program and read operations. The memory cells may be organized or arranged into arrays, two-dimensionally or three-dimensionally, and connected to bias lines, typically referred to as word lines and bit lines. In some three-dimensional memory arrays, the word lines are configured as planar structures referred to as word line plates.
Voltage generation circuitry configured to generate the voltages used to bias the memory cells is typically located on the same die as the memory cells. Also located on the die is decoder circuitry that selectively routes certain voltages to certain word lines and bit lines so that particular memory cells can be programmed or data can be read from particular memory cells. The decoder circuitry may be separated into a row decoder that routes voltages to word lines and a column decoder that routes voltages to bit lines.
In three-dimensional memory architecture, conductive tracks route voltages from the row decoder to word lines. Increased numbers of word lines may require an increased number of tracks. Due to space constraints, increasing the number of word lines may require reducing the size or pitch of the tracks in order to fit the existing and increased number of tracks in the same amount of area. However, reducing the pitch may be costly and undesirable. Thus, ways to reconfigure the components of a memory die to account for increased numbers of word lines may be desirable.